Keheng Huang

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As the feature size of FPGA shrinks to nanometers, SRAM-based FPGAs are more vulnerable to soft errors. During logic synthesis, reliability of the design can be improved by introducing logic masking effect. In this work, we observe that there are a lot of not-fully occupied look-up tables (LUTs) after logic synthesis. Hence, we propose a functional(More)
As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze soft error rate (SER) only at the physical level, consequently completing the design with suboptimal soft(More)
As the feature size shrinks to the nanometer scale, SRAM-based FPGAs will become increasingly vulnerable to soft errors. Existing reliability-oriented placement and routing approaches primarily focus on reducing the fault occurrence probability (node error rate) of soft errors. However, our analysis shows that, besides the fault occurrence probability, the(More)
It is challenging to manage the thermal behavior of many-core microprocessors while still keeping them running at high performance since the control complexity increases as the core number increases. In this article, a novel hierarchical dynamic thermal management method is proposed to overcome this challenge. The new method employs model predictive control(More)
As IC technology advances, leakage current induced static power has become the major obstacle for chip to achieve high performance. Fast estimation of full-chip static power is difficult because static power depends nonlinearly on temperature. In this paper, we propose a new fast full-chip static power estimation method. The new method uses Taylor expansion(More)
As integrated circuit technology advances, we are now facing the utilization wall of the chip, which prevents us from turning on all the cores at the same time and leads to dark silicon. In order to maximize performance without violating thermal threshold for dark silicon chips, we propose a new power budgeting and dynamic thermal management scheme.(More)
Model predictive control (MPC) based dynamic thermal management (DTM) is effective in managing temperature and power of multi-core systems at runtime. However, due to its centralized structure, such method has poor scalability. In this work, we propose a distributed MPC based DTM method, by dividing the full chip thermal model into submodels and decoupling(More)
As the feature size and threshold voltage reduce, leakage power dissipation becomes an important concern in SRAM-based FPGAs. This work focuses on reducing the leakage power in routing resources, and more specifically, the leakage power dissipated in the used part of FPGA device, which is known as the active leakage power. We observe that the leakage power(More)
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