Keerti Vyas

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Output of SRAM memory circuit is very small i.e. in few milli volts. While reading logic 1 sometimes it is read as logic 0. Due to this malfunctioning of circuit, problem of hazards occur. To overcome this problem we use sense amplifiers. The work of sense amplifier is to sense low power signal from bit line of SRAM memory circuit and amplify the small(More)
In this paper, an efficient method of partial product reduction is analysed. there are a number of techniques for partial product reduction it can be use of Wallace and Dadda schemes or can be use of compressor. Here we have studied a number of techniques for partial product reduction and came to a conclusion that compressors are better among them and we(More)
Adders play a vital role in various applications that need fast arithmetic operations. Square root carry select adder is among the fast adders and also has the possibilities of modification. This paper presents the implementation of proposed Square root carry select adder using MCML technique which results in reduced area and power. Analysis is done on the(More)
The effect on transistors when maximum collector-emitter voltage under condition base is open (vceo), maximum collector-base voltage under condition emitter is open (vcbo), maximum collector-emitter voltage under condition base is shortened (vces) and maximum collector-base voltage under condition emitter is shortened (vcbs) ratings are got exceeded in two(More)
MOS current mode logic (MCML) is an emerging logic family which is gaining attention due to its high speed of operation, robust performance and presence of mere switching noise as compared to the CMOS logic family. In this paper we have compared universal gates using MCML and conventional CMOS in terms of power and propagation delay at 16-nm Technology(More)
In this paper, a comparison is done between MOS Current Mode Logic (MCML) and Complementary metal Oxide Semiconductor (CMOS) circuits operating in low power application. It is found that MCML logic circuits exhibit a decrease in delay and so decrease in overall power delay product compared with CMOS circuits. The tested inverter are optimized for low power(More)
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