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- Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
- 1997 Proceedings of IEEE International Conference…
- 1997

We propose a novel algorithm to rapidly identify untestable delay faults using pre-computed static logic implications. Our fault-independent analysis identifies large sets of untestable faults, if any, without enumerating them. The cardinalities of these sets are obtained by using a counting algorithm that has quadratic complexity in the number of lines.… (More)

We propose a segment delay fault model to represent any general delay defect ranging from a spot defect to a distributed defect. The segment length, L, is a parameter that can be chosen based on available statistics about the types of manufacturing defects. Once L is chosen, the fault list contains all segments of length L and paths whose entire lengths are… (More)

- Gordon Gammie, Alice Wang, +14 authors Uming Ko
- ISSCC
- 2008

- Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
- 31st Design Automation Conference
- 1994

We propose a linear complexity method to estimate robust path delay fault coverage in digital circuits. We adopt a path counting scheme for a true-value simulator that uses flags for each signal line. These ags determine the new path delay faults detected by the simulated vector pair. Experimental results are presented to show the effectiveness of the… (More)

- Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
- VLSI Design
- 1995

|We develop new statistical techniques for delay fault analysis. True value simulation is performed using a multi-value logic system describing signal states of two consecutive vectors. Signal statistics are used to estimate transition probabilities and observabilities. These allow us to estimate detection probabilities and the coverage for transition… (More)

We propose a new statistical technique for estimating fault coverage in combinational circuits. Our method requires fault-free simulation of a random sample of vectors from the test vector set. Fault coverage is computed from controllabilities and observabilities both deened as probabilities and the method is applicable to any fault model like… (More)

- Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
- VLSI Design
- 1996

A recently published method computes path delay fault coverage from the count of the number of path faults newly sensitized by a simulated vector pair. Such an estimate is pessimistic since several paths may share a set of lines. In this paper, we present a continuum of approximate methods, approaching exact fault simulation, for a tradeoo between accuracy… (More)

- Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
- Proceedings of International Conference on…
- 1996

Lucent TechnologiesWe propose an efficient combinational circuit simulation technique for the recently proposed segment delay fault model. After simulation of a vector pair, activated segments are traced using a depth-first search. A segment numbering scheme finds the number of faults to be simulated. A labeling technique generates edge labels to compute a… (More)

- Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel
- IEEE Trans. on CAD of Integrated Circuits and…
- 1997

A recently proposed method obtains path delay fault coverages by estimating the count of the number of tested faults instead of actually enumerating them. The estimate become pessimistic when several paths share a set of lines. In this communication, we present a continuum of improved approximations for the counting method, approaching exact fault… (More)

- Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
- IEEE Trans. on CAD of Integrated Circuits and…
- 1995

We develop a new statistical technique for estimating delay fault coverage in combinational circuits. True value simulation is performed for a sample of vector pairs chosen randomly from the test set. Transition probabilities and observabilities are estimated from the simulation data. These allow us to estimate fault detection probabilities per vector pair.… (More)