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A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase detector and automatic frequency locking technique is described. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase error. The frequency acquisition loop utilizes the data(More)
A 2 25-Gb/s receiver for 100-Gb Ethernet (100 GbE) has been implemented in 65-nm CMOS technology. A new regulation mechanism is applied to the limiting amplifier to minimize its gain and bandwidth variations. Two low-power full-rate CDRs (with a built-in clock generator) and a high-speed 2:5 DMUX circuit are integrated. Although only two channels are(More)
Applications of high resolution videos have great potential for H.264/AVC. However, due to the multi-frame motion estimation and large search range (SR) requirement, the ultra high system bandwidth becomes the challenge for the plateform based video codec. In this paper, a hybrid-mode embedded compression (EC) is proposed. Two different strategies are(More)
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