—A 2 25-Gb/s receiver for 100-Gb Ethernet (100 GbE) has been implemented in 65-nm CMOS technology. A new regulation mechanism is applied to the limiting amplifier to minimize its gain and bandwidth variations. Two low-power full-rate CDRs (with a built-in clock generator) and a high-speed 2:5 DMUX circuit are integrated. Although only two channels are… (More)
A linear CDR circuit  manifests itself in easy modeling and minimal activity on phase adjustment under locked condition. However, linear PDs face a speed limitation at around 10Gb/s, primarily because of the required pulsewidth comparison and finite flip-flop CK-to-Q delay. Parallelism could relax the stringent speed requirement, but it also introduces… (More)
—A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase detector and automatic frequency locking technique is described. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase error. The frequency acquisition loop utilizes the data… (More)
The ever growing bandwidth requirement for novel server technologies including multi-core processing, virtualization, and networked storage leads to multi-channel Internet connectivity such as 100GbE. Among the proposed standards , those with 4 channels (e.g., 100GBASE-ER4) are selected to arrive at a reasonable component count in discrete and photonic… (More)
A novel ranging method utilizing modulated clock to count the time of flight (ToF) has been proposed. Substantially reducing the hardware and software complexity, this transceiver prototype achieves ranging resolution of less than 1.3mm while consuming only 50mW from a 1.2V supply.
Applications of high resolution videos have great potential for Frame Buffer H.264/AVC. However, due to the multi-frame motion estimation and large search range (SR) requirement, the ultra high system I Enmbedded I bandwidth becomes the challenge for the plateform based video I Bitstream I codec. In this paper, a hybrid-mode embedded compression (EC) I is… (More)