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Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future memory architectures to satisfy the ever-increasing demands on performance, power, and cost. This paper introduces CACTI-3DD, the first architecture-level integrated power, area, and timing modeling framework for 3D die-stacked off-chip DRAM main memory. CACTI-3DD(More)
OBJECTIVE This study used resting-state functional MRI (fMRI) to evaluate regional and network alterations in patients with Parkinson's disease (PD) with and without depression. METHOD We recruited 29 patients with PD with depression (PD-Dep), 30 patients with PD without depression (PD-NDep), and 30 normal controls. All participants underwent(More)
Retinoic acid receptors (RARs) are reported to mediate the effects of retinoid acid and participate in the maintenance of normal hippocampal function during embryonic and postnatal stages. RARalpha is the only one that has been reported to be continuously expressed among RARs in the CA1-CA3 areas of the hippocampus, at both the mRNA and the protein level.(More)
We propose a method for image segmentation based on a neural oscillator network. Unlike previous methods, weight adaptation is adopted during segmentation to remove noise and preserve significant discontinuities in an image. Moreover, a logarithmic grouping rule is proposed to facilitate grouping of oscillators representing pixels with coherent properties.(More)
Semi-supervised learning concerns the problem of learning in the presence of labeled and unlabeled data. Several boosting algorithms have been extended to semi-supervised learning with various strategies. To our knowledge, however, none of them takes all three semi-supervised assumptions, i.e., smoothness, cluster, and manifold assumptions, together into(More)
DRAM memory is a major contributor for the total power consumption in modern computing systems. Consequently, power reduction for DRAM memory is critical to improve system-level power efficiency. Fine-grained DRAM architecture [1, 2] has been proposed to reduce the activation/ precharge power. However, those prior work either incurs significant performance(More)
This paper introduces CACTI-P, the first architecture-level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTI-P supports modeling of major leakage power reduction approaches including power-gating, long channel devices, and Hi-k metal gate devices. Because it accounts for(More)