Kazuyuki Tanimura

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This paper proposes a new ASIC design flow using latch retiming and random clock-gating to cope with power analysis side-channel attacks. We cast the side-channel attack problem as a combination of retiming and clock-gating problems and solve the problems using only existing EDA tool chains. In particular, we achieve light weight time-shifting obfuscation(More)
—Coarse-grained reconfigurable arrays (CGRAs) are a promising class of architectures conjugating flexibility and efficiency. Devising effective methodologies to map applications onto CGRAs is a challenging task, due to their parallel execution paradigm and constrained hardware resources. In order to handle complex applications, it is important to devise(More)
—Differential Power Analysis (DPA) side-channel attacks pose serious threats for embedded system security. WDDL was proposed as a countermeasure that can be incorporated into a conventional ASIC design flow using standard cells. However, our spice simulations show that DPA attacks on WDDL still leak secret keys to adversaries despite the doubled area and(More)
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