Kazuyuki Maruo

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We have designed an FFT processor based on the 2-stage cached-memory architecture, which integrates 552,000 transistors within an area of 2.8 x 2.8 mm<sup>2</sup> with CMOS 0.35&mu;m triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensional FFT in 23.2 &mu;sec and a 2-dimensional one is only(More)
Summary form only given. We introduce a new image recognition processor using a run-time reconfiguration (RTR) technology. A phase impulse response function (PIRF) is employed as an application for evaluating the performance of RTR architecture. By utilizing the RTR architecture effectively, a complicated image processing application such as PIRF can be(More)
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