Kazuyuki Hirakawa

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This paper describes the logic simulation system and the design verification method for logic design, timing analysis, and testing for VLSI. The integrity of test and network data on a logic design stage must be kept in LSI testing in the final verification stage. In dealing with consistency, emphasis is placed on the discrepancy between the real time(More)
This paper describes a timing analysis system (ACTAS: ACcurate Timing Analysis System). This system analyzes the logical behaviors of VLSI. It verifies timings at flip-flops and detects timing errors. Then, it calculates path delays of the partial combinational circuits generating the errors. If they do not satisfy timing constraints, the system detects(More)
This description is intended for the purpose of relating a brief history of the development of the design automation system in our OKI Electric Industry Co., Ltd. and an outline of the design automation system used at present in our company; it relates specially an introduction of the package design system which is one of the subsystems in the design(More)
Because most LSI layout systems use the Channel Assignment method for routing, they have disadvantages in which block outlines, terminal positions, and placement of blocks are restricted for some reasons and layers with the multilayer routing are used ineffectively. We have successfully developed the LSI layout system that handles up to polygon blocks with(More)
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