Kazuyoshi Torii

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In conventional systems of fingerprint authentication for personal identification, identification rates are reduced when the surface of the fingerprint input device is soiled or damaged by contact. Moreover, 2-value information on ridges and valleys is fundamentally insufficient for evasion of impersonation (cheating). We have examined the possibility of(More)
Gate stacks consisting of a sub-1nm equivalent oxide thickness (EOT) high-k gate dielectric and a metal gate electrode are required for low operation power (LOP) devices in the hp45 node and beyond (1). Although it is difficult to reduce the EOT of a gate stack without degrading mobility, it has recently been demonstrated that this difficulty could be(More)
INTRODUCTION THE semiconductor industry that has witnessed such remarkably sustained and rapid growth for more than 40 years is now in the early years of the 21st century beginning to undergo a fundamental change in the way further performance gains will be achieved. To shed light on this development, this paper reviews the current state of research and(More)
1. Introduction HfSiON is considered the most promising candidate of gate dielectrics for hp65 node LSTP devices due to its high mobility [1-2]. Sub-1nm EOT high-k gate dielectrics are required for LOP devices in hp45 node and beyond [3]. However, the k-value of HfSiON is 16 at most. In order to obtain sub-1nm EOT, the physical thickness of HfSiON must be(More)
In personal authentication systems (PAS) using fingerprints, there is a decline in authentication accuracy because of the dirt on the contact surface and a problem on which a contact surface deteriorates with the present input equipment. We have already examined the possibility of non-contact fingerprint authentication to address these problems. In this(More)
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