Kazuya Tanigawa

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1. Introduction Exploitation of parallelism on the instruction or program-thread level is a widely used method for improving processor performance. To support the continuing trend towards higher parallelism, access ports and entry numbers of the processor's register file must be increased sufficiently. For instance, a processor design which supports(More)
Aiming toward a compact high- throughput reconfigurable architecture, we propose the reconfigurable processor DS-HIE. In order to achieve the characteristics of compactness and high-throughput, the DS-HIE architecture executes operations following a bit-serial computation scheme and adopts a Benes network as its routing resource. Implementing bit-serial(More)
We have developed a compiler for dynamic reconfigurable processor based on VLIW model. VLIW model fetches and executes one configuration data as VLIW instruction. For this model, our compiler schedules mapping elements as operations and live variables in program, with consideration of hardware resources. Next, place-and-route procedure places and routes the(More)
Recently, register files in highly parallel superscalar processors tend to have large chip area and many access ports. This trend causes problems with chip-size, access time and power consumption. As one of the approaches for solving these problems, researchers have proposed several methods using a multi-bank register file instead of multi-port register(More)
In our research, we have proposed a reconfigurable architecture 'PARS' for general purpose. For developing software assets required as a general purpose processor, the PARS architecture introduces an I-PARS execution model as an ideal execution model for coarse-grained reconfigurable processors. The I-PARS execution model is based on an execution model of(More)
In this study, we developed and implemented a placement and routing algorithm for a new switch-block-free fine-grain reconfigurable device, called MPLD, as an evaluation environment of MPLD's ability to realize sequential circuits. An MPLD consists of an array of multiple-output LUTs (MLUTs), which work as logic elements and/or routing elements, and has no(More)