Kazutami Arimoto

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This paper describes a novel TCAM architecture with associated embedded DRAM. The design concept improves the soft error immunity by 6 digits, and also resolves the critical problems of the look-up table maintenance of TCAM. The proposed architecture in this paper is especially attractive for realizing soft-error immune, high-performance TCAM chips.
A heterogeneous multicore SoC (System on a Chip) has been developed for HD (high-definition) multimedia applications that require secure DRM (digital rights management). The SoC integrates three types of processors: two specific-purpose accelerators for a cipher and a high-resolution video decoding; one general-purpose accelerator (MX: Matrix processor);(More)
Ternary CAMs (TCAMs) are becoming increasingly important for realizing networking applications such as address classification or packet filtering. Unfortunately, conventional static TCAMs have three critical problems to be addressed: (i) large chip size, (ii) high power dissipation, and (iii) low yield caused by the lack of an efficient redundancy(More)
In recent year, robust and scale invariant feature extraction algorithms such as SIFT, SURF, and U-SURF are frequently utilized for image recognition. While U-SURF[1] algorithm is robust and scalable to extract interest points and their features, it requires processes in many regions that are scattered in an image. It is difficult for the algorithm to(More)