Kazutami Arimoto

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This paper describes a novel TCAM architecture with associated embedded DRAM. The design concept improves the soft error immunity by 6 digits, and also resolves the critical problems of the look-up table maintenance of TCAM. The proposed architecture in this paper is especially attractive for realizing soft-error immune, high-performance TCAM chips.
Ternary CAMs (TCAMs) are becoming increasingly important for realizing networking applications such as address classification or packet filtering. Unfortunately, conventional static TCAMs have three critical problems to be addressed: (i) large chip size, (ii) high power dissipation, and (iii) low yield caused by the lack of an efficient redundancy(More)
In recent year, robust and scale invariant feature extraction algorithms such as SIFT, SURF, and U-SURF are frequently utilized for image recognition. While U-SURF[1] algorithm is robust and scalable to extract interest points and their features, it requires processes in many regions that are scattered in an image. It is difficult for the algorithm to(More)
We have proposed a power-aware, high-performance, dependable communication link using PCI Express as a direct communication device, referred to as PEARL, for application in a wide range of parallel processing systems from high-end embedded system to small-scale high-performance clusters. In the present study, we describe the structure and function of a(More)
SUMMARY This paper describes a novel TCAM architecture designed for enhancing the soft-error immunity. An associated embedded DRAM and ECC circuits are placed next to TCAM macro to implement a unique methodology of recovering upset bits due to soft errors. The proposed configuration allows an improvement of soft-error immunity by 6 orders of magnitude(More)