In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their computer-aid design (CAD) for intellectual property (IP) cores in system large-scale integration (LSI). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The… (More)
FPGA fault detection consumes a great deal of test time compared with ASICs because FPGAs have complex structures. Re-placement and re-routing must be performed to avoid fault points, which causes an increase in recovery time and degrades performance. Therefore, we propose a fault detection method and develop placement and routing tools to avoid fault… (More)
Generally, a programmable LSI such as an FPGA is difficult to test as compared to an ASIC. There are two major reasons for this. One is that automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a novel FPGA architecture… (More)
FPGA 3 A B CMUX; Multiplexer 1 Fig. 1 Fault tolerance using FPGA reconfiguration.
The most widely used open-source field-programmable gate array (FPGA) placement and routing tool is VPR, which can define the target FPGA, perform placement and routing, and report area and timing information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, for most newly developed FPGA architectures, VPR cannot support them… (More)
Recently, it has been progressively recognized that gene expression is regulated by histone methylation status, which is dynamically modulated by histone methyltransferases (HMTs) and histone demethylases (HDMs). In the past decade, many HMTs and HDMs were identified and their biological and biochemical functions have been characterized. As with other… (More)