Kazuaki Murakami

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This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way predicted, instead of accessing all the ways in a set, the energy consumption can be reduced. This paper shows that the way-predicting set-associative cache improves the ED(More)
In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. Frequent refreshes increase power consumption. Also, they disturb normal DRAM accesses leading to performance degradation. In order to overcome this problem, we propose several DRAM refresh architectures. The basic(More)
Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom instructions (CIs) are usually extracted from critical portions of applications. It may not be possible to meet all of the RFU constraints when CIs are generated. This paper addresses(More)
Graphics processing units (GPUs) provide significant improvements in performance and performance-perwatt as compared to traditional multicore CPUs. This energy-efficiency of GPUs has facilitated the use of GPUs in many application domains. Albeit energy efficient, GPUs consume non-trivial power independently of CPUs. Therefore, we need to analyze the power(More)
To improve the performance of embedded processors, an effective technique is collapsing critical computation subgraphs as application-specific instruction set extensions and executing them on custom functional units. The problem with this approach is the immense cost and the long times required to design a new processor for each application. As a solution(More)
This paper presents a task scheduling method for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable SRAMs under real-time constraints. A mixed integer programming model has been built for minimizing vulnerability under real-time constraints. Experimental(More)
With power consumption being a first-order constraint of microprocessors, they are required to achieve high performance within a strictly limited power budget. For example, the capping of peak power consumption is strongly desired for large-scale data centers and vast high-performance computing machines. In the future, many-core processors are expected to(More)
Many real-world embedded systems employ a preemptive scheduling policy in order to satisfy their realtime requirements. However, most System-Level Design Languages (SLDLs) which were proposed up to now, such as SpecC, do not explicitly support modeling of preemptions. This paper proposes techniques for modeling xed-priority preemptive multi-task systems in(More)