Kayoko Seto

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Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper presents a boosted word line voltage scheme, where an active bodybiasing controlled boost transistor generates a pulsed word line voltage by capacitive coupling only when(More)
Inductor design is investigated for battery charger used in plug-in hybrid vehicles. The inductor is designed to be implemented at the input and output parts of prototype charger (operation at 250 kHz) under development. Circuit simulations revealed inductor resistances at DC, 60 Hz and 500 kHz are the most dominant factors determining inductor efficiency.(More)
Instability of SRAM memory cells derived from aggressive technology scaling has been recently one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-1V, it unfortunately results in degradation of write margins. In order to assist the write operation, we address a new memory(More)
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