Kaustav Banerjee

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Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be(More)
Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect(More)
This paper presents a detailed scaling analysis of the power supply distribution network voltage drop in DSM technologies. The effects of chip temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration(More)
This paper provides an overview of ULSI interconnect scaling trends and their implications for thermal, reliability and performance issues simultaneously. It shows how interconnect scaling requirements for deep sub-micron (DSM) technologies cause increasing thermal effects. The paper then examines the impact of thermal effects on both interconnect design(More)
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], interconnects become extremely resistive and,(More)
In IC designs which incorporate multiple power supply voltages, the interfacing of signals between blocks with different power supplies can be achieved through I/O buffer circuits, which demand high-performance as well as ESD protection for the inputs and outputs. High performance buffers are also desirable for intra-chip interfacing for technologies that(More)
The problem of testing equality of means of a bivariate normal distribution on the basis of a sample of size n has been considered when the labels of the observations are either missing or not known. The problem may arise in many applied settings, especially in genetics. Classical likelihood ratio test fails here because of identifiability problems. We(More)
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