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Using radiolabeled microspheres, spinal cord blood flow was measured after spinal subarachnoid injections of 3.1- to 12.5-nmol doses of somatostatin through either indwelling i.t. catheters or acutely inserted intervertebral needles. With either injection technique, somatostatin caused significant dose-dependent reductions in thoracic and lumbosacral blood(More)
  • A Yamazaki, N Okumura, K Dosaka, M Kumanoya
  • 1996
A fully synchronous circuit for embedded DRAMs is presented. It realizes accurate DRAM timing control, and easy timing adjustment. Using the circuit, software switching of the control timing is realized without difficulty. Providing handshake signals to on-chip memory-controller simplifies the memory-controller circuit in a CPU embedded DRAM. 1.(More)
This paper describes a novel TCAM architecture with associated embedded DRAM. The design concept improves the soft error immunity by 6 digits, and also resolves the critical problems of the look-up table maintenance of TCAM. The proposed architecture in this paper is especially attractive for realizing soft-error immune, high-performance TCAM chips.
Ternary CAMs (TCAMs) are becoming increasingly important for realizing networking applications such as address classification or packet filtering. Unfortunately, conventional static TCAMs have three critical problems to be addressed: (i) large chip size, (ii) high power dissipation, and (iii) low yield caused by the lack of an efficient redundancy(More)
SUMMARY This paper describes a novel TCAM architecture designed for enhancing the soft-error immunity. An associated embedded DRAM and ECC circuits are placed next to TCAM macro to implement a unique methodology of recovering upset bits due to soft errors. The proposed configuration allows an improvement of soft-error immunity by 6 orders of magnitude(More)
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated on 130nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100ms at 80/spl deg/C. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional(More)