Kary Chien

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The poly pillar is a type of defect found in 0.18 /spl mu/m logic based processes, which induces severe yield impact and high temperature operating life (HTOL) test failures. The root cause is the poor quality of SiON growth on the gate-poly layer. The non-uniform grain size makes the etching rate different, and thus induces poly pillars formed after poly(More)
In this paper, tiny in-line defects which correlated with chip low yield were investigated. A procedure which has optimum use of FIBs with different function to prepare ultra-thin TEM sample to analyze tiny defects has been proposed, which help prepare overlap free TEM sample in tiny defect analysis process. TEM /EELS /EFTEM have been performed in tiny(More)
This paper reports the research of applying the worst stress condition of thick gate oxide LDMOSFET hot carrier reliability. Based on electrical characteristic and hot carrier degradation investigation, the worst stress condition selection and failure mechanism are discussed and then the reasonable stress condition is proposed in this paper.
Reliability assessment is a key step in ensuring the quality of a product. As semiconductor technology continues to evolve, the reliability test process also complicates, involving engineers and technical assistants responsible for different test tasks. In this paper, we propose a design of a comprehensive Reliability Management and Index System that(More)
In this paper, PVC method with high energy incident beam was adopted to locate gate oxide defect, instead of conventional low-energy PVC which has low efficiency and accuracy when the poly gate has large size. Under high-energy condition, the potential difference is obvious and the defect can be easily found.
This paper reports the optimized focused-ion-beam (FIB) sample preparation methods for transmission electron microscopy (TEM) analysis, which can prepare two samples at one time for 45nm and below technology nodes. The experimental results showed that these methods can help to reduce the cycle time, decrease the cost and improve the sample quality availably.
Static Random Access Memory (SRAM) array is routinely designed in IC chip during process development. Its' high density and addressable structure allows for better defect isolation and faster feedback of process performance. Hence, identification the root cause of SRAM bit failure is very important for process corrections and yield improvement. This paper(More)
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