Karthik Duraisami

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The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network(More)
The existence of non-uniform thermal gradients on the substrate in high performance IC's can significantly impact the performance of global on-chip interconnects. This issue is further exacerbated by the aggressive scaling and other factors such as dynamic power management schemes and non-uniform gate level switching activity. In high-performance systems,(More)
We present a low-overhead solution to tackle the delay increase caused by Negative Bias Temperature Instability (NBTI), which has emerged as the most critical reliability issue in sub-90nm technology nodes. The proposed solution consists of using special type of registers, called soft-edge flip-flops (SEFFs), which allow to compensate for the delay(More)
Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non-negligible impact on delay and reliability is getting significant attention lately. One of the principal factors affecting designs today is timing criticality, which, in today’s(More)
High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control(More)
Pulse-encoded buses, (i.e., in which a transition is encoded as a pulse) have recently emerged as an effective solution to solve crosstalk issues in global interconnects, since they suppress transitions in opposite directions by construction. As a side effect, this also reduces energy, since coupling capacitances in deep-submicron technologies are larger(More)
Enabled by technology scaling, ultra low-voltage de1.OE+06 vices have now found wide application in modern VLSI circuits. While low-voltage implies reduced dynamic power, it also signifies 1.OE+05 increased leakage power, as lower supply voltages are usually paired with lower threshold voltages in order to preserve circuit 1.OE+04 speed. This originates an(More)
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