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This paper describes the design and implementation of a fully pipelined 64-point Fast Fourier Transform (FFT) in programmable logic. The FFT takes 20-bit fixed point complex numbers as input and after a known pipeline latency produces 20-bit complex values representing the FFT of the input. It is designed to allow continuous input of samples and is(More)
Two of the most critical tasks when designing a portable wireless neural recording system are to limit power consumption and to efficiently use the limited bandwidth. It is known that for most wireless devices the majority of power is consumed by the wireless transmitter and it often represents the bottleneck of the overall design. This paper compares two(More)
This paper presents a powerful and flexible Digital Signal Processing (DSP) architecture based on the Texas Instruments TMS320VC33 DSP and high speed PCI bus. The DSP board provides a convenient, flexible means to test signal processing algorithms in real-time hardware. Algorithms implemented for several research projects include Normalized Least Mean(More)
This paper presents a powerful new low power wireless system for sampling multiple channels of neural activity based on Texas Instruments MSP430 microprocessors and Nordic Semiconductor's ultra low power high bandwidth RF transmitters and receivers. The system's development process, component selection, features and test methodology are presented.
— In this paper, we present a design for a wearable DSP system that is capable of processing various neural-to-motor translation algorithms. The system first acquires the neural data through a high speed data bus in order to train and evaluate our prediction models. Then via a widely used protocol, the low-bandwidth output trajectory is wirelessly(More)
Transversal adaptive filters for digital signal processing have traditionally been implemented into DSP processors due to their ability to perform fast floating-point arithmetic. However, with its growing die size as well as incorporating the embedded DSP block, the FPGA devices have become a serious contender in the signal processing market. Although it is(More)
In this paper, we present a design for a wearable computational DSP system that alleviates the issues of a previous design and provides a much smaller and lower power solution for the overall BMI goals. The system first acquires the neural data through a high speed data bus in order to train and evaluate prediction models. Then it wirelessly transmits the(More)
A design challenge of portable wireless neural recording systems is the tradeoff between bandwidth and power consumption. This paper investigates the compression of neuronal recordings in real-time using a novel discriminating Linde-Buzo-Gray algorithm (DLBG) that preserves spike shapes while filtering background noise. The technique is implemented in a low(More)