Karl-Heinz Diener

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This paper offers an Internet-based environment forenhancing problem-specific design flows with test patterngeneration and fault simulation capabilities. AutomaticTest Pattern Generation (ATPG) and fault simulation toolsat structural and hierarchical levels available at geographicallydifferent places running under the virtual environmentusing the MOSCITO(More)
The World Wide Web has opened up entirely novel ways of teaching and learning. To use these new chances, Germany’s Fraunhofer Gesellschaft (FhG) has launched the implementation of the so-called Fraunhofer Knowledge & Learning Network (FKN). This project is mainly aimed at providing graduates, scientists, engineers and also students with latest skills in(More)
The Web-based education methodology provides new chances and challenges to adopt interdisciplinary expertise needed for mastering the design processes in key technologies as electronics and micro-electro-mechanical systems (MEMS). Simulation should be an integral part in teaching, understanding and design of complex systems. In this paper four courses are(More)
This paper describes an environment for internetbased collaboration in the field of design and test of digital systems. Automatic Test Pattern Generation (ATPG) and fault simulation tools at behavioral, logical and hierarchical levels available at geographically different places running under the virtual environment using the MOSCITO system are presented.(More)
Basically, integrated piezo-resistive sensing elements exhibit parasitic effects that have to be suppressed as necessary. To ensure the proper function of such integrated elements design-driven modeling and simulations have to be performed. This kind of modeling and simulation is extremely useful for determining operation characteristics and verifying(More)
A novel FPGA design flow combined with automated hierarchical test pattern generation was developed and experimented on a real FPGA circuit for telecommunication. A hierarchical test generator for digital systems described in VHDL is presented. Both, register-transfer (RT) and gate level descriptions are used. Decision diagrams are exploited as a uniform(More)