Kaoru Kawamura

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Recently, simulation and/or formal verification in pre-silicon verification cannot accomplish the whole system-level verification with exhaustive input data and run-time because of lack of sufficient speed and logic capacities. Consequently, post-silicon validation, such as in-circuit debugging, becomes increasingly important. In this paper we propose a(More)
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. It provides a common database for delay calculation, logic optimization, placement, and routing tools so that they can work and interact closely. We present results on industrial(More)
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