Kamran Zarrineh

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While the IEEE P1500 standards working group is on the verge of recommending a standard test interface for "non-mergeable" cores, a need was felt to adopt a standard methodology to achieve easy test interoperability for "non-merged" core (RTL, gate level) integration. A task force was formed under the P1500 working group investigating this issue and came up(More)
Given a set of memory array faults the problem of computing an optimal march test that detects all speci-ed memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive march test is deened for each primitive memory fault. We show that march tests(More)
This paper describes a technology independent test synthesis framework to enhance the testability of embedded memories, cores and chips using extended LSSD boundary scan methodology. Extended LSSD boundary scan reuses functional storage elements and therefore introduces minimal test logic overhead and delay. Automatic insertion of this DFT methodology is(More)
The development of two programmable memory BIST architectures is first reported. A memory synthesis framework which can automatically generate, verify and insert programmable as well as non-programmable BIST units is developed as a vehicle to efficiently integrate BIST architectures in today's memory-intensive systems. Custom memory test algorithms could be(More)
—Given a set of memory array faults the problem of computing a compact March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests(More)