Kamran Saleh

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This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. The library includes clock generators and(More)
Asynchronous circuits already have shown their benefits. The main drawback is the lack of powerful CAD and layout generation tools limiting the widespread use of the asynchronous methodology. QDI asynchronous circuits are known as a powerful category of asynchronous circuits targeting performance and power driven design. In this paper we addressed standard(More)
This paper focuses on a clock generation scheme for implementation of GALS circuits on commercial FPGAs which are mostly synchronous. Previously overlooked timing problems of existing pausible clock generators are explored and a novel clock generator is introduced. To validate the proposed solution we implemented the clock generator and a simple port(More)
Asynchronous microprocessors are more flexible to adapt to physical parameters, and have lower power consumption than synchronous microprocessors. In this paper we will introduce the design of an asynchronous microprocessor (V8-uRISC) and explore its design process compared to synchronous design. The processor is synthesized by Persia, an automatic tool for(More)
The complexity of digital design and time-to-market have arose many challenges in synchronous design methodology; the need for high frequency and low skew clock distribution with its profound effect on final circuits take a lot of time and implementation cost. Asynchronous design methodology by eliminating global clock and replacing synchronization with(More)
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