Kameswar Rao Vaddina

Learn More
Three-dimensional IC technology offers greater device integration and shorter interlayer interconnects. In order to take advantage of these attributes, 3D stacked mesh architecture was proposed which is a hybrid between packet-switched network and a bus. Stacked mesh is a feasible architecture which provides both performance and area benefits, while(More)
The emerging three-dimensional integrated circuits (3D ICs) offer a promising solution to mitigate the barriers of interconnect scaling in modern systems. In order to exploit the intrinsic capability of reducing the wire length in 3D ICs, 3D NoC-Bus Hybrid mesh architecture was proposed. Besides its various advantages in terms of area, power consumption,(More)
This paper presents a novel virtual-channel (VC) sharing technique for NoC architecture. The proposed architecture improves the utilization of resources to enhance the performance with minimal overheads. A heuristic approach towards the proper VC sharing strategy is proposed, which is performed by an adaptive algorithm that configures the VC sharing based(More)
As the number of cores increases thermal challenges increase thereby degrading performance and reliability. We approach this challenge with an on-line distributed thermal sensing and monitoring method which is based on the use of thermal sensors. In this work, we propose an approach for the strategic placement of thermal sensors in the multicore systems(More)
As the number of cores increases thermal challenges increase, thereby degrading the performance and reliability of the system. We approach this challenge with a self-timed thermal monitoring method which is based on the use of thermal sensors. Since leakage currents are sensitive to temperature and increase with scaling, we propose the use of a leakage(More)
In this work, an efficient hybridization architecture to optimize power consumption and system performance of Hybrid NoC-Bus 3D mesh is proposed. Hybrid NoC-Bus 3D mesh is a feasible architecture which takes advantage of the short inter-layer wiring delays, while suffering from inefficient intermediate buffers. To address this issue, we propose a mechanism(More)