Kambiz Rahimi

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We propose an empirical simulation model for p-channel floating-gate MOS synapse transistors. Because our model requires only a transistor and controlled sources, and does not use the MOSFET’s channel potential in its description, we can apply the model in any SPICE circuit simulator. The model parameters derive from simple oxide-current measurements. We(More)
Minimizing peak power decreases the probability of failure due to hot carrier effects and electromigration. It also reduces the maximum IR voltage drop, the magnitude of substrate noise, and packaging costs. In mobile applications, minimizing peak power can help reduce the battery size. In synchronous circuits the peak power draw is correlated with clock(More)
This paper introduces Adaptive Delay Sequential Elements (ADSEs). ADSEs are registers that use nonvolatile, floating-gate transistors to tune their internal clock delays. We propose ADSEs for correcting timing violations and optimizing circuit performance. We present an ADSE circuit example, system architecture, and tuning methodology. We present(More)
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