Kamal Chaudhary

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With the shrinking of feature size on silicon the coupled ca-pacitance between adjacent wires is contributing a significant factor to the interconnect delay, which already dominates the circuit performance. In the near future coupled capacitance could contribute as much as 50-75% to the interconnect delay which has been largely ignored by performance(More)
We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (which capture arrival time – gate area tradeoffs) at all(More)
We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (which capture gate area – arrival time tradeoffs) at all(More)
Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consideration of design performance. Timing-driven mode requires that a designer specify performance constraints and then produces a performance-optimized layout solution. The task of generating(More)