Kamal Chaudhary

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With the shrinking of feature size on silicon the coupled ca-pacitance between adjacent wires is contributing a significant factor to the interconnect delay, which already dominates the circuit performance. In the near future coupled capacitance could contribute as much as 50-75% to the interconnect delay which has been largely ignored by performance(More)
We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (which capture arrival time – gate area tradeoffs) at all(More)
We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (which capture gate area – arrival time tradeoffs) at all(More)
This paper presents a placement-driven technology mapping procedure based on fuzzy delay curves. The fuzziness has been introduced to deal with the inherent vagueness in wiring loads (derived from a dynamically updated placement) and used by the mapper to calculate the signal arrival times. In the process we describe a number of fuzzy operations which are(More)
The HIV-1 Nef protein has the ability to down regulate important molecules at the immune synapse. These include class I and class II (Human Leukocyte Antigen) HLA on the Antigen Presenting Cells (APC). The receptors in these molecules consist of SH-3 domain and their interaction with the HIV-1 Nef is critical. Therefore, it is important to inhibit this(More)