• Publications
  • Influence
LFSR Based Stream Ciphers Are Vulnerable to Power Attacks
TLDR
We show that the state of an n-bit LFSR can be determined by making O(n) power measurements and propose a simple countermeasure for the SCA. Expand
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Shakti-T: A RISC-V Processor with Light Weight Security Extensions
TLDR
This work presents a unified hardware framework for handling spatial and temporal memory attacks. Expand
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A syllable based statistical text to speech system
TLDR
A statistical parametric speech synthesis system uses triphones, phones or full context phones to address the problem of co-articulation. Expand
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A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks
TLDR
We propose PEASE, a Programmable Event-driven processor Architecture for SNN Evaluation. Expand
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The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency
TLDR
We show that Software Transactional Memory (STM) systems can perform better than locks for workloads where a significant portion of the running time is spent in the critical sections. Expand
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GANDALF: A Fine-Grained Hardware–Software Co-Design for Preventing Memory Attacks
TLDR
We present Gandalf, a compiler assisted hardware extension for the OpenRISC processor that thwarts all forms of memory-based attacks. Expand
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ProBLeSS: A Proactive Blockchain Based Spectrum Sharing Protocol Against SSDF Attacks in Cognitive Radio IoBT Networks
TLDR
We propose one such protocol called Proactive Blockchain based Spectrum Sharing (ProBLeSS) protocol which leverages a blockchain to provide security against SSDF attacks in CR-IoBT networks. Expand
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Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing
TLDR
We use input toggle minimization as a means to minimize a circuit’s power dissipation during at-speed stuck-at testing under the Combinational State Preservation scan (CSP-scan) Design-For-Testability (DFT) scheme. Expand
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A low-bit rate segment vocoder using minimum residual energy criteria
TLDR
In speech coding, segment vocoders offer good intelligibility at low bit rates. Expand
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SHAKTI-MS: a RISC-V processor for memory safety in C
TLDR
In this paper, we present Shakti-MS, a lightweight RISC-V processor with built-in support for both temporal and spatial memory protection. Expand
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