Kairshik Roy

Learn More
We propose process variation tolerant circuit techniques for robust digital subthreshold design. We present an 8times8 process-tolerant FIR filter, working in both super-threshold and subthreshold regions featuring adaptive beta-ratio modulation and integrated level converters. Ultra-dynamic voltage scaling (UVDS) enables the filter operation at 85 mV(More)
In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. The proposed optimization method reduces subthreshold leakage (by 82%) and gate leakage (by 33%)(More)
Most wireless and hand-held gadgets work in burst mode, and the performance demand varies with time. When the performance requirement is low, the supply voltage can be dithered and the circuit can enter from superthreshold region to subthreshold region (V<sub>dd</sub> &lt; V<sub>T</sub>). Such ultra dynamic voltage scaling (UDVS), where the supply voltage(More)
SRAM is likely to remain the largest, leakiest and most process-sensitive circuit block on chip. FinFET, a width-quantized, quasi-planar, double-gate technology, has emerged as the most likely candidate to replace classical technologies around the 45nm node. This paper studies the impact of FinFET design choices on device and SRAM circuit metrics to(More)
The present paper proposes the SOI-MISISFET (Silicon on insulator-Metal insulator semiconductor insulator semiconductor FET) structure for the leakage current reduction and low power applications. Performance analysis of SOI-MISISFET has been carried out in this paper and the device is compared with that of conventional MOSFET and MISISFET structures. For(More)
Cell stability and tolerance to process variation are of primary importance in subthreshold SRAMs. We propose a DTMOS based 6T SRAM suitable for subthreshold operation. For variation tolerant memory peripheral circuitry, we apply beta-ratio modulation technique. DTMOS SRAM array fabricated in 90 nm technology operates down to 135 mV consuming 0.13 muW at(More)
  • 1