Kai Schleupen

Learn More
Drawing on neuroscience, we have developed a parallel, event-driven kernel for neurosynaptic computation, that is efficient with respect to computation, memory, and communication. Building on the previously demonstrated highlyoptimized software expression of the kernel, here, we demonstrate TrueNorth, a co-designed silicon expression of the kernel.(More)
We report a proof-of-concept demonstration of 2Gbps uncompressed HDTV transmission using a 60-GHz SiGe radio chipset. We took a single-carrier approach with a usual DQPSK modulation scheme, assuming an LOS environment, and implemented the system with FPGAs. At the same time, in order to take care of more frequent sync/burst errors in high-data-rate(More)
Modern FPGAs' parallel computing capability and their ability to be reconfigured make them an ideal platform to build accelerators for supercomputing systems. As a multi-core processor, the recently announced Cell Broadband EngineTMl offers tremendous computing power. In this paper, we introduce a prototype system that combines these two types of computing(More)
This paper describes the hardware and software ecosystem encompassing the brain-inspired TrueNorth processor – a 70mW reconfigurable silicon chip with 1 million neurons, 256 million synapses, and 4096 parallel and distributed neural cores. For systems, we present a scale-out system loosely coupling 16 single-chip boards and a scale-up system tightly(More)
Drawing on neuroscience, we have developed a parallel, event-driven kernel for neurosynaptic computation, that is efficient with respect to computation, memory, and communication. Building on the previously demonstrated highly-optimized software expression of the kernel, here, we demonstrate TrueNorth, a co-designed silicon expression of the kernel.(More)
Increasing demands on end-to-end solution performance has lead to a generation of workload optimized systems and appliances, with tightly integrated hardware and software delivering substantial improvements over general purpose architectures. Among the many challenges encountered in designing an appliance, the most complex one is making hardware and(More)
In this paper we provide a detailed description of a Field Programmable Gate Array (FPGA) based reconfigurable system which has been used in the development of a System on a Chip (SoC) processor and corresponding applications targeted for network computing appliances. The complexity of the processor, in terms of number of hardware threads (64), integrated(More)
Drawing on neuroscience, we have developed a parallel, event-driven kernel for neurosynaptic computation, that is efficient with respect to computation, memory, and communication. Building on the previously demonstrated highly optimized software expression of the kernel, here, we demonstrate True North, a co-designed silicon expression of the kernel. True(More)
  • 1