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- C. S. Selvanayagam, J. H. Lau, Xiaowu Zhang, S. Seah, K. Vaidyanathan, T. C. Chai
- IEEE Transactions on Advanced Packaging
- 2009
Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5 times 10-6/degC) is a few times higher than that of… (More)
- C. S. Selvanayagam, J. H. Lau, Xiaowu Zhang, S. Seah, K. Vaidyanathan, T. C. Chai
- 2008 58th Electronic Components and Technology…
- 2008
Most of TSVs are filled with the copper, even siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5x10-6/degC) is a few times higher than that of… (More)
- Yen Yi Germaine Hoe, Tang Gong Yue, +4 authors K. Vaidyanathan
- 2009 11th Electronics Packaging Technology…
- 2009
In this paper, the effect of TSV (Through Silicon Via) parameters on the equivalent thermal conductivity of TSV interposer and the effect of the TSV interposer on the thermal performance of the… (More)
- Gong Yue Tang, Siow Pin Melvin Tan, +5 authors Kok Chuan Toh
- IEEE Transactions on Components and Packaging…
- 2010
In this paper, an integrated liquid cooling system for 3-D stacked modules with high dissipation level is proposed. The fluidic interconnects in this system are elaborated and the sealing technique… (More)
- Tai Chong Chai, Xiaowu Zhang, +15 authors Yoshio Tsutsumi
- IEEE Transactions on Components, Packaging and…
- 2011
The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional… (More)
- Navas Khan, Seung Wook Yoon, +5 authors K. Vaidyanathan
- IEEE Transactions on Advanced Packaging
- 2008
Stacking of many functional chips in a 3-D stack package leads to high heat dissipation. Therefore, a new platform technology is required to assemble chips vertically and remove the heat effectively.… (More)
- Navas Khan, S.W. Yoon, +4 authors K. Vaidyanathan
- 56th Electronic Components and Technology…
- 2006
Stacking of many functional chips in a 3D stack package leads to high heat dissipation. Therefore a new platform technology is required to assemble chips vertically and remove the heat effectively. A… (More)
- Ying Ying Lim, Xianghua Xiao, +8 authors Shiguo Liu
- IEEE Transactions on Advanced Packaging
- 2010
With the increasing demand for system integration to cater to continuously increasing number of I/Os as well as higher operating frequencies, reconfigured wafer-level packaging, or embedded WLP… (More)
- Xuefen Ong, Soon Wee Ho, +9 authors Zhong Chen
- 2007 9th Electronics Packaging Technology…
- 2007
In this paper, a systematic underfill selection approach has been presented to characterize and identify favorable underfill encapsulants for 21 times 21 mm2 flip chip ball grid array (FCBGA) package… (More)
- Yue Ying Ong, Soon Wee Ho, +12 authors Dong Kyun Sohn
- IEEE Transactions on Components, Packaging and…
- 2011
This paper presents a systematic underfill selection and characterization methods for 21 ×21 mm2 Cu/low-K flip chip packages (65 nm technology) with 150 μm bump pitch. This paper has also correlated… (More)