Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Low-Power Digital Signal Processing Using Approximate Adders
- Vaibhav Gupta, D. Mohapatra, A. Raghunathan, K. Roy
- Computer ScienceIEEE Transactions on Computer-Aided Design of…
This paper proposes logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates the utility of these approximate adders in two digital signal processing architectures with specific quality constraints.
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
- M. Powell, Se-Hyun Yang, B. Falsafi, K. Roy, T. N. Vijaykumar
- Engineering, Computer ScienceInternational Symposium on Low Power Electronics…
- 1 August 2000
Results indicate that gated-V<subscrpt>dd</subscRpt> together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.
Going Deeper in Spiking Neural Networks: VGG and Residual Architectures
- Abhronil Sengupta, Yuting Ye, Robert Y. Wang, Chiao Liu, K. Roy
- Computer ScienceFrontiers in Neuroscience
- 7 February 2018
A novel algorithmic technique is proposed for generating an SNN with a deep architecture with significantly better accuracy than the state-of-the-art, and its effectiveness on complex visual recognition problems such as CIFAR-10 and ImageNet is demonstrated.
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
- S. Mukhopadhyay, H. Mahmoodi, K. Roy
- EngineeringIEEE Transactions on Computer-Aided Design of…
- 21 November 2005
A methodology to statistically design the SRAM cell and the memory organization using the failure-probability and the yield-prediction models and can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
- I. Chang, Jae-Joon Kim, S. P. Park, K. Roy
- Engineering, Computer ScienceIEEE Journal of Solid-State Circuits
- 27 January 2009
A differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability and provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC).
Low-Power CMOS VLSI Circuit Design
Low--Power CMOS VLSI Design and Test of Low--Voltage CMOS Circuits and Low--Energy Computing Using Energy Recovery Techniques.
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
A novel Schmitt trigger (ST) based differential 10-transistor SRAM (static random access memory) bitcell suitable for subthreshold operation and does not require any architectural changes from the present 6T architecture is proposed.
IMPACT: IMPrecise adders for low-power approximate computing
- Vaibhav Gupta, D. Mohapatra, S. P. Park, A. Raghunathan, K. Roy
- Computer ScienceIEEE/ACM International Symposium on Low Power…
- 1 August 2011
This paper proposes logic complexity reduction as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates this concept by proposing various imprecise or approximate Full Adder cells with reduced complexity at the transistor level, and utilizing them to design approximate multi-bit adders.
Carbon-nanotube-based voltage-mode multiple-valued logic design
The geometry-dependent threshold voltage of C NFETs has been effectively used to design a ternary logic family and a SPICE-compatible model of ballistic CNFETs is developed that can account for varying geometries and operating conditions.