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Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
TLDR
Results indicate that gated-V<subscrpt>dd</subscRpt> together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.
Low-Power Digital Signal Processing Using Approximate Adders
TLDR
This paper proposes logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates the utility of these approximate adders in two digital signal processing architectures with specific quality constraints.
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
TLDR
A differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability and provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC).
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
TLDR
A methodology to statistically design the SRAM cell and the memory organization using the failure-probability and the yield-prediction models and can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.
Low-Power CMOS VLSI Circuit Design
TLDR
Low--Power CMOS VLSI Design and Test of Low--Voltage CMOS Circuits and Low--Energy Computing Using Energy Recovery Techniques.
Going Deeper in Spiking Neural Networks: VGG and Residual Architectures
TLDR
A novel algorithmic technique is proposed for generating an SNN with a deep architecture with significantly better accuracy than the state-of-the-art, and its effectiveness on complex visual recognition problems such as CIFAR-10 and ImageNet is demonstrated.
IMPACT: IMPrecise adders for low-power approximate computing
TLDR
This paper proposes logic complexity reduction as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates this concept by proposing various imprecise or approximate Full Adder cells with reduced complexity at the transistor level, and utilizing them to design approximate multi-bit adders.
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
TLDR
A novel Schmitt trigger (ST) based differential 10-transistor SRAM (static random access memory) bitcell suitable for subthreshold operation and does not require any architectural changes from the present 6T architecture is proposed.
Carbon-nanotube-based voltage-mode multiple-valued logic design
Multivalued logic has always attracted the attention of digital system and logic designers. However, the high-performance and low-power CMOS process, which has been developed over the last two
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