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Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
TLDR
This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instrucðtion caches. Expand
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Low-Power Digital Signal Processing Using Approximate Adders
TLDR
We propose various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. Expand
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Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
TLDR
We have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations. Expand
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A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
TLDR
In this paper, we propose a differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability. Expand
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Low-Power CMOS VLSI Circuit Design
TLDR
Low--Power CMOS VLSI Design. Physics of Power Dissipation in CMOS FET Devices. Design and Test of Low--Voltage CMOS Circuits. Expand
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IMPACT: IMPrecise adders for low-power approximate computing
TLDR
We propose various imprecise or approximate Full Adder (FA) cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. Expand
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Going Deeper in Spiking Neural Networks: VGG and Residual Architectures
TLDR
We propose a novel algorithm for generating an SNN with a deep architecture, and demonstrate its effectiveness on complex visual recognition problems such as CIFAR-10 and ImageNet. Expand
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Analysis and characterization of inherent application resilience for approximate computing
TLDR
Approximate computing is an emerging design paradigm that enables highly efficient hardware and software implementations by exploiting the inherent resilience of applications to in-exactness in their computations. Expand
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Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis
TLDR
We examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T-SRAM-array topology. Expand
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TapeCache: a high density, energy efficient cache based on domain wall memory
TLDR
Domain Wall Memory (DWM) is a recently developed spin-based memory technology in which several bits of data are densely packed into the domains of a ferromagnetic wire. Expand
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