K. Mielcarek

Publications44
h-index5
Citations63
Highly Influential Citations2
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Designing LUT-based mealy FSM with transformation of collections of output functions
TLDR
A design method is proposed for LUT-based Mealy FSMs with less amount of LUTs than known from literature methods. Expand
  • 6
  • 1
Designing Moore FSM with unstandard representation of state codes
A design method is proposed for FPGA-based Moore FSMs. The method is based on presentation of state codes as concatenations of codes of classes of pseudoequivalent states and collections of output… Expand
  • 3
  • 1
Logic Synthesis for FPGA-Based Finite State Machines
  • 22
Design of EMB-Based Moore FSMs
TLDR
The chapter deals with design of Moore FSMs based on using embedded memory blocks. Expand
  • 8
Hardware Reduction for Lut–Based Mealy FSMs
TLDR
A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. Expand
  • 10
  • PDF
Twofold State Assignment for LUT-based Mealy FSMs
TLDR
A method is proposed for reducing hardware in LUT-based Mealy FSMs. Expand
  • 1
Design of EMB-based Mealy FSMs with transformation of output functions
TLDR
A design method for EMB-based Mealy FSM based on transformation of collections of output functions into state variables . Expand
  • 5
Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design
  • 1
Designing Moore FSM with extended class codes
A method is proposed for designing LUT-based Moore FSMs. The method is based on splitting the set of classes of pseudoequivalent states. There are given example of design and results of… Expand
  • 1
Twofold state assignment for FPGA-based mealy FSMs
TLDR
A method is proposed for decreasing hardware in FPGA-based Mealy FSMs by partitioning the set of states by classes. Expand
  • 2