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Symbolic model checking
TLDR
Using symbolic model checking techniques it is possible to verify industrial-size finite state systems and models with more than 10120 states have been verified using special techniques.
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Symbolic Model Checking: 10^20 States and Beyond
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Symbolic model checking: an approach to the state explosion problem
TLDR
The symbolic model checking technique revealed subtle errors in this protocol, resulting from complex execution sequences that would occur with very low probability in random simulation runs, and an alternative method is developed for avoiding the state explosion in the case of asynchronous control circuits.
Interpolation and SAT-Based Model Checking
TLDR
In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.
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An interpolating theorem prover
  • K. McMillan
  • Computer Science, Mathematics
    Theor. Comput. Sci.
  • 21 November 2005
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Lazy Abstraction with Interpolants
TLDR
A model checker for infinite-state sequential programs, based on Craig interpolation and the lazy abstraction paradigm, which observes a speedup of up to two orders of magnitude relative to a similar tool using predicate abstraction.
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Applying SAT Methods in Unbounded Symbolic Model Checking
A method of symbolic model checking is introduced that uses conjunctive normal form (CNF) rather than binary decision diagrams (BDD's) and uses a SAT-based approach to quantifier elimination. This…
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A technique of state space search based on unfolding
  • K. McMillan
  • Computer Science
    Formal Methods Syst. Des.
  • 1995
TLDR
A procedure is given for constructing the unfolding of a Petri net, terminating the construction when it is sufficient to represent all reachable markings, and this procedure is applied to hazard and deadlock detection in asynchronous circuits.
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Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits
TLDR
The method presented in this paper is based on unfolding a Petri net into an acyclic structure called an occurrence net, which has a certain advantage over behavior machines method of Probst, which requires a pomset grammar describing tile circuit's behavior to be constructed by hand.
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Theory of latency-insensitive design
TLDR
The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components to design large digital integrated circuits by using deep submicrometer technologies.
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