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Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache
TLDR
In this paper we present a novel STTRAM LLC design that mitigates the long write latency, thereby delivering SRAM like performance while preserving the benefits of high density. Expand
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The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm
TLDR
This paper describes an analytical modeling tool called Bitlet that can be used, in a parameterized fashion, to understand the affinity of workloads to processing-in-memory (PIM) as opposed to traditional computing. Expand
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The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency
TLDR
We show that Software Transactional Memory (STM) systems can perform better than locks for workloads where a significant portion of the running time is spent in the critical sections. Expand
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Characterization of User's Behavior Variations for Design of Replayable Mobile Workloads
TLDR
We analyze the usage of CPUs, GPUs and associated memory operations in real user interactions, and develop microbenchmarks on an automated methodology which describes realistic and replayable test runs that statistically mimic user variations. Expand
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Vorpal: Vector Clock Ordering For Large Persistent Memory Systems
TLDR
We describe a collection of provably correct algorithms for enforcing the persist-order across writes, generated at many different cores, and persisted across numerous different memory controllers. Expand
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To Cache Or To Bypass ? A Fine Balance in The Emerging Memory Technology Era
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Performance Evaluation: Of A Hardware Transactional Memory System
TLDR
The major difficulty in carrying out the performance analysis of a hardware system like Hardware Transactional Memory lies in suitably modeling it. Expand
Thread Synchronization: From Mutual Exclusion to Transactional Memory
TLDR
This paper provides an introductory material on TM, followed by a background of important historical work on synchronization leading to current TM research. Expand