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VTR 7.0: Next Generation Architecture and CAD System for FPGAs
Recent advances in the open source Verilog-to-Routing (VTR) CAD flow are described that enable further research in these areas and release new FPGA architecture files and models that are much closer to modern commercial architectures, enabling more realistic experiments.
The VTR project: architecture and CAD for FPGAs from verilog to routing
The current status and new release of an ongoing effort to create a downstream full-implementation flow of Verilog to Routing is described, and the use of the new flow is illustrated by using it to help architect a floating-point unit in an FPGA, and compared with a prior, much longer effort.
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling
A new version of the VPR toolset is described and illustrated that supports a broad range of single-driver routing architectures, and provides optimized electrical models for a wide range of architectures in different process technologies, including a range of area-delay trade-offs for each single architecture.
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research
- P. Jamieson, K. Kent, Farnaz Gharibian, Lesley Shannon
- Computer Science18th IEEE Annual International Symposium on Field…
- 2 May 2010
Odin II is a framework for Verilog Hardware Description Language (HDL) synthesis that allows researchers to investigate approaches/improvements to different phases of HDL elaboration that have not been previously possible and can be used by ASIC and FPGA researchers for more than basic synthesis.
Hardware Acceleration of BLOB Detection for Image Processing
- A. Bochem, R. Herpers, K. Kent
- Computer ScienceThird International Conference on Advances in…
- 18 July 2010
This paper presents the implementation and evaluation of a computer vision task on a Field Programmable Gate Array (FPGA). As an experimental approach for an application-specific image-processing…
Investigating resource interference and scaling on multitenant PaaS clouds
A mathematical model is proposed that describes CPU allocation per tenant depending on interference from other tenants on the same VM, which is used to make predictions and confirm them in a variety of experimental situations and is evaluated for profiling the resource-intensiveness of cloud applications that uses slowdown in the presence of a resource-intensive cloud burner.
A quantitative analysis of the .NET common language runtime
The effectiveness of brute force attacks on RC4
Preliminary results show that a network of key-checker units implemented on a Xilinx XC2V1000 FPGA using Celoxica DK2 design tools can exploit the speed and parallelism of hardware such that the entire key-space of a 40-bit RC4 encryption can be searched in minutes.
The co-design of virtual machines using reconfigurable hardware
This research demonstrates that using hardware/software co-design as described specifically for virtual machines, the solution can offer performance benefits over a software-only solution and is shown to be dependent upon several factors such as the application itself and the underlying architectural features.
Periodic licensing of FPGA based intellectual property
This work describes a method of licensing IP on FPGAs based on techniques derived from software licensing schemes, and an implementation on a Xilinx Vertex 2 FPGA demonstrates that expiration of FFPA based IP can be achieved.