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- Publications
- Influence
On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits
- K. K. Kim, W. Wang, Ken Choi
- Engineering, Computer Science
- IEEE Transactions on Circuits and Systems II…
- 1 October 2010
TLDR
A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems
- K. K. Kim, Y. Kim
- Engineering, Computer Science
- IEEE Transactions on Very Large Scale Integration…
- 1 April 2009
TLDR
Optimal Body Biasing for Minimum Leakage Power in Standby Mode
- K. K. Kim, Y. Kim
- Engineering, Computer Science
- IEEE International Symposium on Circuits and…
- 27 May 2007
TLDR
On-chip aging prediction circuit in nanometer digital circuits
- Byunghyun Jang, J. Lee, M. Choi, K. K. Kim
- Engineering
- International SoC Design Conference (ISOCC)
- 1 November 2014
TLDR
Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels
- K. K. Kim, Jing Huang, Y. Kim, F. Lombardi
- Computer Science
- IEEE Transactions on Industrial Informatics
- 20 May 2008
TLDR
Efficacy of 6-month pretransplant abstinence for patients with alcoholic liver disease undergoing living donor liver transplantation.
PURPOSE
Questions have been raised regarding the ethics of liver transplantation in patients with alcoholic liver disease (ALD), including the fairness of cadaveric organ allocation to individuals… Expand
On-chip process variation monitoring circuit based on gate leakage sensing
A novel on-chip process-variation monitoring circuit for nanoscale CMOS designs is proposed. The proposed circuit can monitor both global and local variations associated with transistors on an… Expand
Analysis of time dependent dielectric breakdown in nanoscale CMOS circuits
- H. Lee, K. K. Kim
- Materials Science, Computer Science
- International SoC Design Conference
- 1 November 2011
TLDR
On-Chip Delay Degradation Measurement for Aging Compensation
- K. K. Kim
- Materials Science
- 1 April 2015
As technology scales down, it has become one of the most critical issues in aging-tolerant nanoscale MOSFET circuit design to monitor the performance degradation of the circuits under aging stress… Expand
A 32nm and 0.9V CMOS Phase-Locked Loop with Leakage Current and Power Supply Noise Compensation
TLDR
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