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On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits
TLDR
This paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. Expand
  • 96
  • 7
A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems
  • K. K. Kim, Y. Kim
  • Engineering, Computer Science
  • IEEE Transactions on Very Large Scale Integration…
  • 1 April 2009
TLDR
This paper proposes a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. Expand
  • 53
  • 3
  • PDF
Optimal Body Biasing for Minimum Leakage Power in Standby Mode
  • K. K. Kim, Y. Kim
  • Engineering, Computer Science
  • IEEE International Symposium on Circuits and…
  • 27 May 2007
TLDR
This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. Expand
  • 19
  • 2
  • PDF
On-chip aging prediction circuit in nanometer digital circuits
TLDR
This paper proposes a new on-chip aging sensor circuit to predit and detect a circuit failure caused by BTI and HCI aging effects on digital circuits. Expand
  • 7
  • 2
Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels
TLDR
This paper presents a novel modeling analysis of jitter as applicable to testing of serial data channels. Expand
  • 12
  • 2
Efficacy of 6-month pretransplant abstinence for patients with alcoholic liver disease undergoing living donor liver transplantation.
PURPOSE Questions have been raised regarding the ethics of liver transplantation in patients with alcoholic liver disease (ALD), including the fairness of cadaveric organ allocation to individualsExpand
  • 19
  • 1
On-chip process variation monitoring circuit based on gate leakage sensing
A novel on-chip process-variation monitoring circuit for nanoscale CMOS designs is proposed. The proposed circuit can monitor both global and local variations associated with transistors on anExpand
  • 17
  • 1
Analysis of time dependent dielectric breakdown in nanoscale CMOS circuits
  • H. Lee, K. K. Kim
  • Materials Science, Computer Science
  • International SoC Design Conference
  • 1 November 2011
TLDR
The TDDB effects on delay and power of nanoscale CMOS circuits are analyzed using inverter chains and ISCAS85 benchmark circuits. Expand
  • 11
  • 1
On-Chip Delay Degradation Measurement for Aging Compensation
As technology scales down, it has become one of the most critical issues in aging-tolerant nanoscale MOSFET circuit design to monitor the performance degradation of the circuits under aging stressExpand
  • 9
  • 1
A 32nm and 0.9V CMOS Phase-Locked Loop with Leakage Current and Power Supply Noise Compensation
TLDR
This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. Expand
  • 9
  • 1
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