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Implementation of MAC using area efficient and reduced delay vedic multiplier targeted at FPGA architectures
The Multiply-Accumulator (MAC) unit always lies in the critical path that determines the speed of the overall hardware systems. Expand
Delta-sigma buck converter — A design exploration for GSM Wireless systems
A switching regulator that has a delta sigma (ΔΣ) controller is considered as an alternative to provide both power efficiency and better spurious performance. Expand
Advances in Natural and Applied Sciences
In this paper, an implementation of area efficient and reduced delay 64 bit Vedic Multiplier (VM) is proposed. Expand
FPGA implementation of delay optimized single precision floating point multiplier
This paper proposes a IEEE-754 single precision floating point multiplier which handles over flow, under flow and rounding. Expand
Design of area and power efficient full adder in 180nm
This paper presents a high drivability of full adder with less area and power consumption by using both gate diffusion input (GDI) technique and pass transistor logic. Expand
Design of Five Stage CIC Decimation Filter for Signal Processing Applications
With the development of more compact and efficient ways of implementing digital logic on a silicon chip, most of the signal processing is being performed in the digital domain. The design of anExpand
A Novel Rom-less Direct Digital Frequency Synthesizer based on Euler Infinite Series
92 Abstract—The traditional DDFS based on a look up table needs a large sized ROM and it is more complex. This paper deals with a novel ROM-less architecture based on the approximation of Euler’sExpand
Static range testing of ADC
This paper discusses the viability of Time Tick based Built In Self Test (TT BIST) implementation using the binary “hot” values of the Analog to Digital Converter (ADC) output for ADC testing. Expand
A Method for ADC Error Testing and its Compensation in Ratiometric Measurements
A Method for ADC Error Testing and its Compensation in Ratiometric Measurements Errors induced due to ratiometric measurements are discussed and a simplified compensation method to reduce the variousExpand
A delta-sigma based DC to DC converter — A design space exploration
Traditional pulse-width modulation (PWM) in a DC-DC converter offers high efficiency but has large spurs occurring at integer multiples of the clock frequency. An alternate architecture using theExpand