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[2] D. Dobberpuhl et al., " A 200 MHz 64b dual-issue CMOS microprocessor , " IEEE J. A 300 megasamples/s wave digital filter implementation in bit-parallel TSPC circuit technique, " in A high-speed wave digital filter using carry-save arithmetic, " in Proc. ESSCIRC 1987, pp. 43–46. [6] T. G. Noll, " Carry-save architectures for high-speed digital signal(More)
In this paper we describe the design and experimental evaluation of a clocked CMOS adiabatic logic (CAL). CAL, is a dual-rail logic that operates from a single-phase AC power-clock supply in the 'adiabatic' mode, or from a DC power supply in the 'non-adiabatic' mode. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip(More)
Droplet-based programmable processors promise to offer solutions to a wide range of applications in which chemical and biological analysis and/or small-scale synthesis are required, suggesting they will become the microfluidic equivalents of microprocessors by offering off-the-shelf solutions for almost any fluid based analysis or small scale synthesis(More)
A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrates several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally.(More)
A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic(More)