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A new high frequency drain current noise model was developed for MOSFETs under sub-threshold condition. A simple parameter extraction technique is proposed, which utilizes Y-parameter analysis on the RF small-signal equivalent circuit. Good agreement has been obtained between the predicted and measured results up to 20 GHz.
In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology.(More)
In this letter, a universal cascade-based deembedding technique was presented for on-wafer characterization of the RF CMOS device. As compared with existing deembedding approaches, it is developed based on unique combinations of two THRU structures that enable efficient deembedding of fixture parasitics without any inaccurate lumped approximation or(More)
In this letter, a drain current noise model that includes the channel thermal noise and the shot noise generated at the source-bulk junction and the drain-bulk junction is presented. A unified analytical expression is derived to ensure excellent continuity with smooth transition of drain current noise from weak- to strong-inversion regimes, including the(More)
We present in this paper a novel accurate decibel linear control circuit topology for variable gain amplifiers. According to our knowledge, the proposed linear-in-dB control circuit features the simplest control mechanism and topology for current summing or current steering VGAs to date. Based on the proposed circuit topology, a wideband variable gain(More)
This paper presents the high-frequency (HF) noise modeling of an RF MOSFET for a 90-nm technology node. A brief discussion on the noise measurement theory is presented to illustrate the limitation of the noise measurement system. The extracted noise sources were studied for their geometry and biasing dependences and by implementing additional noise sources(More)
An accurate and scalable RF differential inductor design kit is presented in this paper. The RF model in this design kit is accurate and continuous, capable of predicting all the differential inductors in the test element group. Coded into a smart and interactive foundry design kit, this scalable inductor model can be fully exploited to help cope with the(More)
The paper presents a method for improving the phase noise performance of a CMOS quadrature LC oscillator through parasitic compensation. Owing to the parasitic resistance in the inductor, the LC oscillator suffers from a low Q-value, which degrades its phase noise performance. In this design, through the parasitic-compensation method, the LC oscillator will(More)
This paper presents a detailed analysis of the RC polyphase network. A new approach based on very basic principles is used to derive the transfer functions of the RC polyphase network when it is used for quadrature signal generation. The 0deg-phase and 90deg-phase signals' mismatch is described quantitively in this paper. A quadrature signal generator with(More)
In this letter, a unique cascade-parallel based noise de-embedding technique is presented for on-wafer device characterization and modeling. It utilizes two fully shielded THRU line structures and one OPEN structure that enable simultaneously de-embedding of series contact resistance, forward coupling and distributed parasitics of interconnect. Thus, it is(More)