K. S. R. Krishna Prasad

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This paper describes the design of power optimized phase locked loop for frequency synthesis, Clock and Data recovery, carrier synchronization and many more communication and VLSI applications. PLL consist of Phase Frequency Detector, charge pump along with passive low pass filter and wide tuning VCO. A modified ring oscillator with tuning range of 280 MHz(More)
This paper presents a modified folded cascode error amplifier of low dropout (LDO) regulator and a slew-rate enhancement circuit to minimize compensation capacitance and improve transient response. The proposed error amplifier eliminates the tradeoffs between small and large slew-rate that is imposed by the tail-current in conventional error amplifier(More)
An integrated buck converter that operates under low voltage environment with fast transient response is presented. The designed buck regulator employs derivative output ripple voltage for sensing current. It is targeted to be fabricated with 180nm UMC technology at 2MHz switching frequency. The response time is less than 2.2μ Sec. The regulator provides an(More)
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