K. S. J. Pister

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A 900 MHz, ultra-low power RF transceiver is presented for wireless sensor networks. It radiates -6 dBm in transmit mode and has a receive sensitivity of -94 dBm while consuming less than 1.3 mW in either mode from a 3 volt battery. Two of these transceivers have been demonstrated communicating over 16 meters through walls at a bit rate of 20 kbps while(More)
The modeling, simulation, and experimental verification of several MEMS devices are presented. Simulated results include 3D mode analysis, residual stress effects, thermal expansion, nonlinear deflections, time-varying electrostatic forces, process sensitivities, induced currents, and the transient performance in accelerated reference frames. To simulate(More)
A popular physical layer used in wireless sensor networks is the IEEE 802.15.4 standard, which provides for a single coding scheme with constant data rate regardless of channel properties and noise conditions. This paper proposes and simulates a simple steganography method to embed additional information in 802.15.4 data packets when link quality permits,(More)
The design of RF circuits for short-range, low-power wireless communication is discussed. A derivation of optimum link range and transceiver power budget is presented based on simple models for indoor path loss and power vs. performance tradeoffs in a generic transceiver. Design techniques aimed at efficiently reaching these parameters are discussed for(More)
SUGAR is a nodal analysis package for 3D MEMS simulation that owes its heritage and its name to the SPICE family of circuit simulation. SUGAR has undergone the stage of proof-of-concept which showed that nodal analysis was in fact just as accurate and much faster than nite element simulation on many MEMS problems. The upcoming major release of SUGAR is(More)
This paper describes a CMOS imaging receiver for free-space optical (FSO) communication links. The die contains 256 parallel receive channels with -47 dBm optical sensitivity and 30 dB optical dynamic range. Arbitration circuitry multiplexes the data to a common bus. The 1.6 M transistor mixed-signal circuit is realized in 0.25 /spl mu/m CMOS and measures(More)
A novel, three-dimensional 8x 1 micro-Fresnel lens array has been realized by surface micromachining technique; three-dimensional alignment blocks and supporting structures for both the micro-Fresnel lens array and the 8x 1 vertical-cavity surface-emitting laser (VCSEL) array are also realized during the same process. With the help of these(More)
In this paper an equivalent model for floating gate transistor has been proposed for smart dust. Smart dust has an advantage of discrete size with substantial functionality and connectivity so; it will provide new methods to sense and interact with the environment especially in rural areas. Using the floating gate voltage value, capacitive coupling(More)
The attributes of transistors such as length, width or oxide thickness are being scaled down when integrated circuits are fabricated. This process variation becomes important at smaller process nodes as the variation becomes a larger percentage of the full length or width of the device. This transistor sizing causes measurable and predictable variance in(More)
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