K . Preethi

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This paper implements serial data communication using I<sup>2</sup>C (Inter-Integrated Circuit) master bus controller using a field programmable gate array (FPGA). The I<sup>2</sup>C master bus controller was interfaced with MAXIM DS1307, which act as a slave. This module was designed in Verilog HDL and simulated in Modelsim 10.1c The design was synthesized(More)
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