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Today, the price of building a factory to produce submicron size electronic devices on 300 mm Si wafers is over billions of dollars. In processing a 300 mm Si wafer, over half of the production cost comes from fabricating the very-large-scale-integration of the interconnect metallization. The most serious and persistent reliability problem in interconnect(More)
Electromigration of eutectic SnPb flip chip solder joints and their mean-time-to-failure ~MTTF! have been studied in the temperature range of 100 to 140 °C with current densities of 1.9 to 2.75 310 A/cm. In these joints, the under-bump-metallization ~UBM! on the chip side is a multilayer thin film of Al/Ni~V!/Cu, and the metallic bond-pad on the substrate(More)
Twinning has been recognized to be an important microstructural defect in nanoscale materials. Periodically twinned SiC nanowires were largely synthesized by the carbothermal reduction of a carbonaceous silica xerogel prepared from tetraethoxysilane and biphenyl with iron nitrate as an additive. The twinned β-SiC nanowires, with a hexagonal cross section, a(More)
In flip chip package, the majority of heat is from the die side and a temperature gradient builds up from the chip to substrate through the solder joint and underfill. This will induces biased atomic flux from hot end to cold end in the solder. Even in electromigration test vehicle, the joule heating from the Al trace at chip side is also higher than(More)
This paper addresses the issue of delivering power to high performance 3D stacks such as a processor on cache stack. Through Silicon Vias (TSVs) with their associated keep out zones (KOZ) occupy only a small fraction of the die (<;1%) but can cause much larger design inefficiencies in the lower strata. We show that integrating the power TSVs in the thin(More)
In system level electromigration test of 2.5D IC, Joule heating enhanced electromigration failure has been found to occur in redistribution layer in the interposer. In our test samples, there are two redistribution layers (RDL), each between every two levels of solder joints, so there are three levels of solder joints. First, the microbumps connect a Si(More)
We report tensile properties of intermetallic compound (IMC)-based solder joints. A systematic study of the mechanical properties of solder joint covering a broad size spectrum from BGA (ball grid array), flip chip joint, to microbump, which are key components used in 3D IC packaging, has been performed. We found that when the size of solder joint is(More)
As the Moore's law is drawing to an end, there is a growing consensus that 3D stacking of Si integrated circuit chips is necessary to continue the current technological trend. In our work, a test 3D IC structure is successfully achieved and the effect of filler trap on microbump of solder joints will be discussed. In our test samples, the two Si chips are(More)
Nanoditches from selective etching of periodically twinned SiC nanowires were employed to hinder the migration and coalescence of Pd nanoparticles supported on the nanowires, and thus to improve their catalytic stability for total combustion of methane. The results show that the etched Pd/SiC catalyst can keep the methane conversion of almost 100% while the(More)
A metastable phase of Sn has been found to co-exist with ß-Sn in Pb-free SnAg microbumps in 3D integrated circuit (3D IC) technology. Synchrotron microbeam x-ray diffraction, high-resolution TEM imaging and selected-area electron diffraction were used to confirm the metastable phase, which has a orthorhombic lattice, with lattice parameter a = 0.635(More)