K. N. Chiang

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The demands for electronic packages with lower profile, lighter weight, and higher input/ output (I/O) density have led to rapid expansion in flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent demand high I/O density and good reliability characteristics have led to the evolution of ultra high-density non-solder(More)
A novel chip-on-metal structure of the advanced wafer level chip scale package (WLCSP) which has the capability of redistributing the electrical circuit is proposed in this study. In the WLCSP, the solder on rubber (SOR) design expands the chip area and also provides a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE)(More)
Studies have found that fracture strength increases when chip thickness decreases. However, the effect of thickness interacts with the effect of roughness during the manufacturing. Therefore, to understand the individual impact, decoupling the effect of thickness and roughness is important. Consequently, this research focuses on the effect of roughness on(More)
The purpose of this research is to enhance the structure of the 204-pin small outline dual in-line memory module (SODIMM) against the drop impact. According to the JEDEC regulations, the enhancement of PCB clips should be attempted to increase the resistance against drop impact. From high speed camera observation, the SODIMM module is pushed away from the(More)
As we move forward toward the miniaturization of electronic devices, small size, high reliability and good thermal dissipation capability are not only convenient but they are also necessity of the design. However complicated factorial analyses were concurrent with module design, hi this study, a 40-lead modified leadframe "land grid array" (LGA) module(More)
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