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An electrical-optical chip input-output (I/O) interconnection technology called sea of polymer pillars (SoPP) is presented. SoPP provides highly process-integrated and mechanically flexible (compliant) electrical-optical die-to-board interconnections that mitigate thermo-mechanical expansion mismatches. The I/O density of SoPP exceeds 10/sup 5//cm/sup 2/.(More)
The Sea of Polymer Pillars offers highly compliant electrical, optical, and RF wafer-level I/O interconnects at an I/O density larger than 10/sup 5//cm/sup 2/. Dual mode I/O pillars function simultaneously as both electrical and optical interconnects to offer circuit/system designers essentially unlimited I/O bandwidth at potentially the lowest cost.
In recent years interconnecting devices have become primary limits on the performance, energy dissipation, signal integrity, and productivity of gigascale integration (GSI). Opportunities to address the interconnect problem include new materials and processes, reverse scaling, novel microarchitectures, three-dimensional integration, input/output(More)
The authors show that Sea of leads (SoL) is a disruptive paradigm for system-on-a-chip (SoC) because it intends to use wafer-level batch fabrication of ultra high density (>10/sup 4//cm/sup 2/) x-y-z compliant input/output leads and packages as well as wafer level DC/AC testing and burn-in to enhance performance, cost, size, weight, and reliability of a(More)
This paper describes the process and assembly integration of Sea of Leads (SoL) with an Intel chip. A primary goal of the research was to study the issues involved in reconciling the fabrication and assembly requirements of compliant leads, such as SoL, with those of standard semiconductor processes and standard chip assembly techniques. The study was(More)
Compliant interconnects can enable wafer level packages with high I/O density, high reliability and better performances with low cost and small size. A fabrication process for SoL compliant interconnects has been optimized to achieve high yield and compatibility with standard back-end-of-line (BEOL) as well as flip-chip bonding processes. The optimized(More)
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