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This paper proposes an improved soft switched synchronous buck converter in a fixed load condition. The switching energy can be fully recovered during current commutation phase in the gate driver while the diode conduction losses in the low and high side switches can be substantially reduced by employing additional L and C resonant in the circuit. Using(More)
high output power density VHF converter has become important in recent years. This output power density of the converter is experiencing an adverse effect resulted from the applied switching frequency. In addition, the frequency which is higher than 20 MHz will no longer be applicable on the discreet SMT technology hence lowers the output power density.(More)
The analysis of loading effects on Synchronous Rectifier Buck Converter (SRBC) performance using fixed Pulse Width Modulation (PWM) technique is presented in this paper. The main objective of this paper is to analyze the effects of load variations on switching loss, conduction loss and body-diode conduction loss in SRBC circuit. There are three load(More)
The implementation of an independent-duty-cycled high frequency resonant gate driver (RGD) circuit utilizing an inductive coupled linear transformer is proposed and simulated using PSpice circuit simulator. The totem-poled configuration of driving MOSFETs that makes the resonant LC network is used in the proposed RGD circuit. The free-wheeling diodes are(More)
(RGD) circuits operating in very high frequency (VHF) switching is discussed. The specific RGD circuits are normally applied only for certain applications due to their design limitations and drawbacks. The isolation techniques must be considered to avoid mismatch and interruption of signals as well as the dead time delay, size of components and choice of(More)
This paper proposes a new resonant gate driver circuit for a soft switching synchronous buck converter in a fixed load condition. The switching energy can be fully recovered during current commutation phase in the gate driver while the diode conduction losses in the low and high side switches can be substantially reduced by employing additional L and C(More)
This paper discusses about the effects of switching frequency where reduction in losses is significant to the converter's performance. The proposed zero-voltage-switching synchronous buck converter circuit is compared with the conventional synchronous buck converter by applying different frequency ranging from 250 kHz to 1.25 MHz. PSpice simulation is(More)
The performance analysis of the Fixed Duty Ratio (FDR) and Adaptive Gate Drive (AGD) in high frequency gate driver design is analyzed in this paper. FDR is well known for its simplicity. The limitation of this control scheme requires a longer delay time before the next switching can be executed. As for AGD, the delay adjustment can be controlled for(More)
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