K.H. Kuesters

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For the first time, a new DRAM cell layout as the key enabler for future DRAM shrink generations based on deep trench (DT) technologies with a planar array device is presented. The work describes the full integration scheme in 70nm technology and the major technology features of the 'checkerboard (CKB)' layout. The new layout is beneficial for lithography(More)
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