K. G. Sharma

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This paper presents a new low power 2-Bit magnitude comparator using full adder technique. The proposed magnitude comparator (PTL logic) has been compared with existing magnitude comparator (GDI technique). The performance analysis of both magnitude comparators is done on basis of power consumption with respect to input voltage, temperature, and frequency;(More)
Domestication of tomato has resulted in large diversity in fruit phenotypes. An intensive phenotyping of 127 tomato accessions from 20 countries revealed extensive morphological diversity in fruit traits. The diversity in fruit traits clustered the accessions into nine classes and identified certain promising lines having desirable traits pertaining to(More)
In this paper low power full adder using 11 transistors has been proposed. The main idea of design is based on improving the performance of 10 transistor full adder design mentioned in literature by sacrificing a transistor count. While the proposed circuit has negligible area overhead, it has remarkably improved power consumption and temperature(More)
In this paper, a new design of three transistor XOR gate is proposed using Independent Driven Double Gate MOSFET to achieve ultra-low power in sub threshold conduction. The proposed design has been compared with the three transistor XOR implemented using Symmetrical Driven Double Gate MOSFET in sub threshold region. A three transistor XOR gate designed(More)
Many of the today’s real time signal processing algorithm included multiplication as its processing heart. In case of signal and image processing, it mostly used functional unit. In this paper we are simulating different multiplication algorithm with their effective architecture. Also paper introducing new multiplication technique using barrel shifter which(More)
This paper presents post layout simulations of a new 8T full adder cell using a new 3T XOR gate implemented by pMOS transistors only. This proposed design operates efficiently in super threshold region to achieve ultra low power and hence reduced power-delay product (PDP). The proposed design demonstrates its superiority against existing adder in terms of(More)
Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this paper, AND gates with(More)