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We present Eudoxus, a tool for generation of architectural variants for arithmetic soft cores and testing structures targeting a wide variety of functions, operand sizes and architectures. Eudoxus produces structural and synthesizable VHDL and/or Verilog descriptions for: (a) several arithmetic operations including addition, subtraction, multiplication,(More)
This paper presents the design and implementation of a real time face detection system on an embedded reconfigurable platform. Our approach to face detection is based on a skin-segmentation algorithm followed by feature extraction and face verification. Our implementation is done on DMV, a reconfigurable platform with novel features targeting real time(More)
This paper presents the details of a tool that automates the generation of the register fields of a System-On-Chip. The generator requires a single text file as input and produces the synthesizable version of a wide range of registers with different properties. The supported register fields are in one to one correspondence with the fields defined in the UVM(More)
This paper presents the architecture of a system for rapid prototyping of digital circuits that is based on the ALTERA FLEX8000 family reconfigurable set of FPGAs. The interconnection architecture of the system consists of both fixed lines between adjacent FPGAs and shared lines capable of interconnecting more than two devices. The reconfigurable set of(More)
The paper presents the design and development of an E1 Transceiver with specifications posed by the ITU G.703 and ITU G.823 recommendations and INTRACOM S.A. (Hellenic Telecommunications and Electronics Industry, R&D Department). The development procedure is based on the use of standard HDL and fulfills the requirements placed by industry for code(More)
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