Junneng Zhang

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This paper proposes a service-oriented reconfigurable co-processing architecture. The novelty of the architecture is to apply service-oriented concepts to system on chip (SoC) design paradigms and utilizes each processor and IP core as a function unit. Regarded as abstract instructions, tasks can be scheduled to IP core for parallel execution automatically.(More)
Multi-processor system on chip (MPSoC) has been widely applied in embedded systems design. However, it has posed great challenges in designing and implementing prototype chip for diverse applications due to different instruction set architectures (ISA), programming interfaces and software tool chains. In order to solve the problem, we introduce SOA into(More)
This article presents MP-Tomasulo, a dependency-aware automatic parallel task execution engine for sequential programs. Applying the instruction-level Tomasulo algorithm to MPSoC environments, MP-Tomasulo detects and eliminates Write-After-Write (WAW) and Write-After-Read (WAR) inter-task dependencies in the dataflow execution, therefore to operate(More)
Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, with the growing number of processors, interconnect on chip is becoming one of the major bottlenecks of MPSoC architecture. In this paper, we propose a star network based on peer to peer links on FPGA. The star network utilizes fast simplex(More)
Multi-Processor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, it poses a great challenge to design a flexible high-speed network regarding as the growing number of processors. This paper proposes a star network based on peer to peer links on FPGA. The stat network uses fast simplex links (FSL) for(More)
In daily life, we are surrounded by all kinds of data. How to find the relationship between these data has become one of the most challenges before the data scientists. In 2011, David N. Reshef etc. took a great leap on solving this problem. They has proved that maximal information coefficient(mic) is an effective tool to detect different kinds of(More)
This paper proposes a flexible programming model (FPM), which addresses the automatic parallel execution for functional tasks on heterogeneous multiprocessors. Guided by the simply annotated source codes, a front-end source to source compiler is provided to identify the parallel regions and generate the sources codes. A runtime middleware analyzes the(More)
This paper presents a novel data hazards detecting engine, task score boarding, which applies instruction level score boarding algorithm to reconfigurable MPSoC on FPGA for out-of-order task execution. Task score boarding can detect inter-task data dependencies and then assign tasks to different processors or IP cores automatically. When the computing(More)
Heterogeneous multicore platform has been widely used in various areas to achieve both power efficiency and high performance. However, it poses significant challenges to researchers to uncover more coarse-grained task level parallelization. In order to support automatic task parallel execution, this paper proposes a FPGA implementation of a hardware(More)